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ATmega128
This bit is set if the next character in the receive buffer had a Frame Error when received. I.e.
when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the
receive buffer (UDRn) is read. The FEn bit is zero when the stop bit of received data is one.
Always set this bit to zero when writing to UCSRnA.
? Bit 3 – DORn: Data OverRun
This bit is set if a Data OverRun condition is detected. A data overrun occurs when the receive
buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a
new start bit is detected. This bit is valid until the receive buffer (UDRn) is read. Always set this
bit to zero when writing to UCSRnA.
? Bit 2 – UPEn: Parity Error
This bit is set if the next character in the receive buffer had a Parity Error when received and the
parity checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer
(UDRn) is read. Always set this bit to zero when writing to UCSRnA.
? Bit 1 – U2Xn: Double the USART Transmission Speed
This bit only has effect for the asynchronous operation. W rite this bit to zero when using syn-
chronous operation.
W riting this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively dou-
bling the transfer rate for asynchronous communication.
? Bit 0 – MPCMn: Multi-Processor Communication Mode
This bit enables the Multi-processor Communication mode. W hen the MPCMn bit is written to
one, all the incoming frames received by the USART Receiver that do not contain address infor-
mation will be ignored. The transmitter is unaffected by the MPCMn setting. For more detailed
information see “Multi-processor Communication Mode” on page 186 .
USARTn Control and
Status Register B –
Bit
7
6
5
4
3
2
1
0
UCSRnB
Read/ W rite
Initial Value
RXCIEn
R/ W
0
TXCIEn
R/ W
0
UDRIEn
R/ W
0
RXENn
R/ W
0
TXENn
R/ W
0
UCSZn2
R/ W
0
RXB8n
R
0
TXB8n
R/ W
0
UCSRnB
? Bit 7 – RXCIEn: RX Complete Interrupt Enable
W riting this bit to one enables interrupt on the RXC flag. A USART Receive Complete interrupt
will be generated only if the RXCIE bit is written to one, the global interrupt flag in SREG is writ-
ten to one and the RXC bit in UCSRnA is set.
? Bit 6 – TXCIEn: TX Complete Interrupt Enable
W riting this bit to one enables interrupt on the TXCn flag. A USARTn Transmit Complete inter-
rupt will be generated only if the TXCIEn bit is written to one, the global interrupt flag in SREG is
written to one and the TXCn bit in UCSRnA is set.
? Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable
W riting this bit to one enables interrupt on the UDREn flag. A Data Register Empty interrupt will
be generated only if the UDRIEn bit is written to one, the global interrupt flag in SREG is written
to one and the UDREn bit in UCSRnA is set.
? Bit 4 – RXENn: Receiver Enable
W riting this bit to one enables the USARTn Receiver. The Receiver will override normal port
operation for the RxDn pin when enabled. Disabling the Receiver will flush the receive buffer
invalidating the FEn, DORn and UPEn flags.
? Bit 3 – TXENn: Transmitter Enable
189
2467X–AVR–06/11
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